As a conventional A/D converter, for example, Japanese Patent Application Laid-Open No. 9-8662 discloses an encoding circuit for an A/D converter having a bit line divisional buffer, in which bit lines of encoders are divided into plurality such that the number of transistors connected to bit lines is reduced, so as to reduce a precharging time and an encoding time of the encoders.
FIG. 1 shows a conventional encoding circuit, wherein the encoding circuit comprises selection transistors 117 which serves as selection transistor switches for discharging bit lines, code selection signal terminals 118 for controlling the selection transistors 117 by code selection signal, and bit lines 119 to 121, to each of which selection transistors 117 are connected.
The encoding circuit further comprises bit line precharging transistors 115, encoding transistors 116, and a control signal terminal 114 for controlling the precharging transistors 115 by control signals, and the encoding transistors 116 discharge the bit lines 119 to 121, when the selection transistors 117 are turned on. First and second encoders 133 and 134 are composed of the selection transistors 117, the bit lines 119 to 121, the precharging transistors 115 and the encoding transistors 116, respectively.
Encoded signals 135 output from the first encoder 133 are input to first input terminals of a bit line divisional buffer 137 comprising AND circuits 138, and encoded signals 136 output from the second encoder 134 are input to second input terminals of the bit line divisional buffer 137.
In the conventional encoding circuit, a charge loaded on the bit line is decreased by dividing the bit lines into plural encoders, and the logic signals divided into plural groups are synthesized by a single bit line divisional buffer provided at the next stage.
Next, operation of the conventional encoding circuit will be explained.
First, when the control signal input to the control signal terminal 114 becomes to L (low) level, in the first and second encoders 133 and 134, the respective precharging transistors 115 thereof are switched to ON state and the respective encoding transistors 116 thereof are switched to OFF state.
Next, all of the bit lines 119 to 121 of the first and second encoders 133 and 134 are precharged via the precharging transistors 115 by a power source.
During the period when the control signal of the control signal terminal 114 is kept at the L level, data to be converted are transmitted to the code selection signal terminal 118 (P0 to P7), and it is determined whether the respective selection transistors 117 should be switched to ON or OFF state in response thereto. Among the code selection signal terminal P0 to P7, the code selection signal terminal P5 is connected to an encoder (not shown), which encodes all of the 3-bits to be "1".
Then, all of the bit lines 119 to 121 in the first and second encoders 133 and 134 are sufficiently charged, and the states of the respective selection transistors 117 are determined such that the data should be converted into a desired binary code. Thereafter, the control signal input to the control signal terminal 114 becomes to H (high) level, and the selection transistors 117 are switched to ON or OFF state in response to a signal "1" or "0" which is input to the code selection signal terminals P0 to P7, then some of the bit lines are discharged by the selection transistors 117 of the ON state and the encoding transistor 116 which is turned on.
Encoded signals 135 (D10 to D12) and 136 (D20 to D22) are output from the first and second encoders, respectively. Finally, the encoded signals 135 and 136 are input to the bit line divisional buffer 136, and signals synthesized thereat are output as a desired binary code signal from digital signal output terminals 122 (G0 to G2).
However, according to the conventional bit line divisional encoding circuit, there are following disadvantages.
The first disadvantage is that when data to be converted are provided in a certain order, some of bit lines are unnecessarily precharged, so that the electric power is excessively consumed.
The second disadvantage is that since divided data should be synthesized, time delay is occurred at a logic signal-sythesizing circuit.
The third disadvantage is that an operation state requires two steps of precharging period and active (discharging) period. Accordingly, for the purpose of conducting a converting operation with a higher speed, time duration of the active period in which the data is fixed can not help being excessively reduced, or a converting operation speed for the whole A/D converting circuit is determined by the structure of the encoding circuit.
The fourth disadvantage is that, since the bit lines may be at floating state in some case during the active period, it becomes difficult to apply the encoding circuit to operation requiring only the low-speed conversion, thereby reducing freedom of circuit design.